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Current AffairsEconomy

Union Cabinet Approves Semicon 2.0 Worth ₹1.27 Lakh Crore to Scale India's Chip Ecosystem

Friday, 17 July 20262 min read1

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📝 AI-generated analysis for exam preparation. This is original educational content curated for competitive exam aspirants.

EconomyDeep Analysis

In this article

Why This MattersBackgroundKey PointsAnalysisWay Forward

Why This Matters

The Union Cabinet, chaired by Prime Minister Narendra Modi, cleared Semicon 2.0 on 15 July 2026 with an outlay of ₹1,27,500 crore, marking the second phase of India's flagship push to build a self-reliant semiconductor ecosystem. The approval came bundled with the ₹62,500 crore Mobile Phone Manufacturing Scheme (MPMS) and the National Investment Policy for Urea 2026, taking the day's total Cabinet outlay to roughly ₹2.19 lakh crore.

Semicon 2.0 is the direct successor to the India Semiconductor Mission (ISM) launched in December 2021, under which 12 projects worth ₹1.64 lakh crore have already been approved, including India's first commercial fab at Dholera, Gujarat. The new phase widens the incentive net from fabrication alone to the full value chain — design, equipment and materials, assembly-testing, R&D and skilled manpower.

For aspirants preparing for UPSC, UPPSC, MPSC, and other state PSC exams, this topic is directly relevant for GS Paper 3 (Industrial Policy, Science & Technology, Infrastructure) and has repeatedly appeared as a source-based question on India's electronics and semiconductor push since ISM 1.0's launch.

Background

India's semiconductor push began with the Semicon India Programme approved in December 2021 with an outlay of ₹76,000 crore, later revised upward, aimed at reversing decades of near-total import dependence for chips used in everything from smartphones to defence systems. The programme was anchored by the India Semiconductor Mission (ISM), a Special Purpose Vehicle under the Ministry of Electronics and Information Technology (MeitY), which evaluates and disburses fiscal support to fabs, display units and ATMP/OSAT (Assembly, Testing, Marking and Packaging / Outsourced Semiconductor Assembly and Test) facilities.

Under ISM 1.0, 12 projects across Gujarat, Assam, Uttar Pradesh, Odisha and Punjab were cleared, including Tata Electronics' fab in Dholera and its OSAT unit in Assam, and Micron's ATMP facility in Sanand. However, India's chip design talent — a significant share of the world's chip designers work out of Indian R&D centres — remained under-monetised domestically, with most output serving foreign fabless companies rather than an Indian ecosystem. Semicon 2.0 is designed to close this gap by extending direct incentives to design-linked and equipment/materials segments for the first time.

Key Points

Who and When

  • Approved by the Union Cabinet chaired by PM Narendra Modi on 15 July 2026
  • Nodal ministry: Ministry of Electronics and Information Technology (MeitY), implemented via the India Semiconductor Mission (ISM)

Outlay and Structure

  • Total outlay: ₹1,27,500 crore under Semicon 2.0
  • Six pillars: (1) Chip Design, (2) Machines & Materials, (3) Fabs, (4) ATMP/OSAT, (5) R&D, (6) Talent Development
  • Builds on ISM 1.0's 12 approved projects worth ₹1.64 lakh crore

Companion Approvals Same Day

  • Mobile Phone Manufacturing Scheme (MPMS): ₹62,500 crore over FY2026-27 to FY2031-32
  • MPMS incentive structure: 2.25%–5% sales-linked incentive, up to 1.5% extra for domestic component sourcing, 3% for in-house design/R&D
  • MPMS targets: ₹39 lakh crore cumulative production, ₹15 lakh crore in exports, 60,000 direct jobs
  • National Investment Policy for Urea 2026 (NIPU 2026): incentivises nine new gas-based urea plants for self-reliance
  • Infrastructure package: ₹10,998 crore Varuna river elevated corridor and ₹14,448 crore Ganga river elevated corridor in Varanasi; Paradeep-Haridaspur rail doubling (₹2,542 crore) and Dangoaposi-Rajkharsawan fourth line (₹1,365 crore)

Strategic Rationale

  • Reduces India's near-total dependence on imported chips for electronics, automotive, telecom and defence applications
  • Targets India's large share of the world's chip-design workforce for domestic value capture
  • Aligns with the broader Atmanirbhar Bharat and Make in India frameworks

Implementation

  • Disbursed as fiscal support/incentives to approved private-sector applicants, evaluated by the ISM Special Purpose Vehicle
  • Total day's Cabinet outlay across all approvals: approximately ₹2,19,353 crore

Analysis

Political and Constitutional Dimensions Industrial licensing and the control of specified industries fall under Entry 52 of the Union List (Seventh Schedule) — 'industries, the control of which by the Union is declared by Parliament by law to be expedient in the public interest' — operationalised through the Industries (Development and Regulation) Act, 1951. This Union-domain classification is why schemes like Semicon 2.0 are designed and funded centrally rather than by individual states, even though states compete to host the physical fabs and ATMP units through their own land and power incentives.

Economic and Financial Dimensions At ₹1,27,500 crore, Semicon 2.0 is one of the largest single-sector industrial outlays in recent years, and — combined with MPMS — signals a shift from assembly-stage electronics manufacturing (as under the original Production-Linked Incentive scheme) toward deeper value-chain capture. Analysts note that fabs alone do not guarantee returns without a domestic design and equipment ecosystem, which is the specific gap Semicon 2.0's design and machines/materials pillars target.

Social Dimensions The talent-development pillar is aimed at converting India's large pool of electronics and VLSI engineering graduates into a domestic chip workforce, potentially reducing high-skill emigration from a sector where Indian talent has historically served foreign fabless firms remotely. Job-creation claims (60,000 under MPMS alone) will need independent verification as projects mature.

Governance and Administrative Dimensions Implementation runs through the India Semiconductor Mission SPV under MeitY, which appraises applications, disburses incentives in tranches tied to milestones, and coordinates with state governments on land, power and water allocation for fab-grade infrastructure — a model that has drawn criticism for slow disbursement timelines under ISM 1.0.

International Perspective Semicon 2.0 arrives as global semiconductor supply chains diversify away from over-concentration in Taiwan and China (the 'China Plus One' trend), with India competing against Vietnam, Malaysia and Mexico for the same investment pool. The scheme is also India's answer to the US CHIPS Act and the EU Chips Act, positioning India as a 'trusted' alternative node in an increasingly securitised global chip supply chain.

Way Forward

  1. Fast-track land and power allocation clearances for approved fab and ATMP sites to avoid the multi-year delays seen under ISM 1.0.
  2. Publish milestone-linked disbursement data periodically so incentive claims can be tracked against actual capacity commissioned.
  3. Expand design-linked incentives to smaller fabless startups, not only large integrated players, to broaden the ecosystem base.
  4. Strengthen VLSI and semiconductor curricula at IITs, NITs and polytechnics to feed the talent-development pillar with job-ready graduates.
  5. Coordinate state-level incentive packages (land, power, water) with the central scheme to avoid destructive inter-state bidding wars.
  6. Build downstream demand-side linkages — telecom, automotive and defence PSUs sourcing domestically fabricated chips — to de-risk fab investments.
  7. Practice on PSCPrep: Attempt previous year questions on India's semiconductor and electronics policy for free — search 'Semicon 2.0 India semiconductor mission' in the PYQ section at PSCPrep to practise UPSC and state PSC questions on this topic without creating an account.

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  • •Prelims angle: factual question on key term, scheme, or institution mentioned in this article.
  • •Mains angle: short analytical answer on policy impact, challenges, and way forward.

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